George Toms synthesis
1_bit_adder
Design Parameters:
Max. gates
Design Parameters:
Project name:
1_bit_adder
Input names, input vectors:
C0,A0,B0
01010101,00110011,00001111
Output names, output vectors:
C1,S0
Output orders:
original
reverse
reverseBut0
Gates sets and (pole accelerators):
nand4,nor4,and4,or4,xor2,xnor2 (0,2,3)
nand3,nor3,and3,or3,xor2,xnor2 (0,2)
nand2,nor2,and2,or2,xor2,xnor2 (0)
nand4,nor4,xor2,xnor2 (0,2,3)
nand3,nor3,xor2,xnor2 (0,2)
nand2,nor2,xor2,xnor2 (0)
nand4,nor4,and4,or4 (0,2,3)
nand3,nor3,and3,or3 (0,2)
nand2,nor2,and2,or2 (0)
nand4,nor4 (0,2,3)
nand3,nor3 (0,2)
nand2,nor2 (0)
nor4 (0,2,3)
nor3 (0,2)
nor2 (0)
nand4 (0,2,3)
nand3 (0,2)
nand2 (0)
Optimization:
delay
gates
transistors
area
power
fan-out
levels
wires
none
Gates:
Truth Table:
Truth Table:
Design results:
Design results:
Selected Gate-Level Netlist:
Show Netlist
Gate-Level Netlist:
Gate-Level Netlist:
Export to Verilog and VHDL
Show Schematic
Export Schematic
Show Racing
Schematic:
Schematic:
Racings:
Racings:
